A variety of different new memory cell technologies have been developed and are being developed as replacements for magnetic and switched transistor memories, such as hard disk drives, and random access memory of various kinds. Some of these new memory types have limitations on the number of write cycles they allow to any particular memory cell. In order to maximize the service life of these memory devices, a wear-leveling system is used to level the wear across the memory cells distributing writes through-out the device. The wear leveling may be in an operating system, a software application, a memory controller, or a memory module.
PCM (Phase Change Memory) and PCMS (Phase Change Memory and Switch) are NVM (Non-Volatile Memory) technologies with performance characteristics suitable for use as a memory in a variety of different computing systems. PCMS provides fast reads and writes and can allow a single memory cell or a small group of cells to be written at one time. This makes PCMS suitable not just for replacing conventional mass storage memory but also short term and buffer memory. Currently DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) are used for these high speed applications. However, like NAND and other types of flash memory, PCMS has a limit to the total number of write cycles that can be performed to any one storage cell.
Traditional wear-leveling schemes applied to NAND create problems when applied to a typical main memory application. Main memory is accessed frequently using small granularity reads and writes and even small latency increases have a significant performance impact on the overall system. Traditional wear-leveling schemes for NAND use large blocks of memory cells for wear leveling and require considerable overhead in processing the wear leveling operations. Such schemes also require a large quantity of metadata to track the used of each cell block. Such schemes therefore become expensive for main memory applications.
With NAND based storage sub-systems very large wear leveling blocks are used together with explicit wear-leveling. Explicit wear leveling requires keeping track of the total write-count to every NAND block. If the NAND based storage is used as a mass storage system, such as for a hard disk drive replacement, then the performance requirements are significantly lower than for main memory. However, such large wear-level blocks are not usable with memory subsystems that are particularly sensitive to latency. This might include graphics and processing buffers and short term cache memory subsystems. In addition, since the write traffic in a main memory or similar application typically consists of many small granularity writes that are randomly distributed, it is very difficult to track these writes using large memory cell blocks. Finally, explicit wear-leveling requires that the total wear-count be maintained and updated on each write. This becomes very complex for smaller blocks in a memory application. In order to explicitly track the writes for each cell most existing NAND memory systems use an intelligent micro-controller and firmware for wear leveling.